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W9725G6IB
Operating Burst Read Current
All banks open, Continuous burst reads, I OUT = 0 mA;
BL = 4, CL = CL (IDD), AL = 0;
I DD4R
t CK = t CK(IDD) ; t RAS = t RASmax(IDD) , t RP = t RP(IDD) ;
155
135
mA
1,2,3,4,5,6
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0;
I DD4W
t CK = t CK(IDD) ; t RAS = t RASmax(IDD) , t RP = t RP(IDD) ;
170
150
mA
1,2,3,4,5,6
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
t CK = t CK(IDD) ;
I DD5B
Refresh command every t RFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
145
135
mA
1,2,3,4,5,6
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
I DD6
CKE ≦ 0.2 V, external clock off, CLK and CLK at 0 V;
Other control and address inputs are FLOATING;
4
4
mA
1,2,3,4,5,6
Data bus inputs are FLOATING.
Operating Bank Interleave Read Current
All bank interleaving reads, I OUT = 0mA;
BL = 4, CL = CL (IDD), AL = t RCD(IDD) - 1 x t CK(IDD) ;
I DD7
t CK = t CK(IDD) , t RC = t RC(IDD) , t RRD = t RRD(IDD) , t RCD =
t RCD(IDD) ;
195
170
mA
1,2,3,4,5,6
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
Notes:
1.
2.
3.
4.
V DD = 1.8 V ± 0.1V; V DDQ = 1.8 V ± 0.1V.
I DD specifications are tested after the device is properly initialized.
Input slew rate is specified by AC Parametric Test Condition.
I DD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS .
6. Definitions for I DD
LOW = V in ≦ V IL (ac) (max)
HIGH = V in ≧ V IH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at V REF = V DDQ /2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Publication Release Date: Oct. 23, 2009
- 41 -
Revision A04
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